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a5f8c720f4
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a5f8c720f4 | ||
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ad4f5e7962 |
@ -1121,14 +1121,14 @@ let clock_unification_pass verbose debug ast =
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| EVar([TBool], var) -> acc, e
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| EConst([TBool], cons) -> acc, e
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| EMonOp([TBool], MOp_not, e) -> count_not e (acc + 1)
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| _ -> raise (PassExn "verify_when failure")
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| _ -> acc, e
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in
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let verify_when e1 e2 =
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let n1, var1 = count_not e1 0
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and n2, var2 = count_not e2 0 in
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if n1 mod 2 <> n2 mod 2 || var1 <> var2 then
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raise (PassExn "clock unification failure")
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raise (PassExn "verify_when failure")
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in
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let get_var_name var = match var with
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@ -1243,14 +1243,9 @@ let clock_unification_pass verbose debug ast =
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snd n.n_local_vars); (* Initializing local variables to Unknown clock *)
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List.iter (fun v -> Hashtbl.replace known_clocks v Base) (
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snd n.n_outputs); (* Initializing outputs to base clock *)
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try
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begin
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iter_til_stable n.n_equations;
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(* catch potential errors and test for unification *)
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check_unification n;
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Some n
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end
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with
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| PassExn err -> (verbose err; None)
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end
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in node_pass compute_clock_node ast
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